High-Density 3D Pyramid-Shaped Microelectrode Arrays for Brain-Machine Interface Applications

RÉSUMÉ Les dispositifs médicaux dédiés aux enregistrements des activités neuronales et à la stimulation de tissus nerveux sont appelés interfaces cerveau-machines. Ils offrent un potentiel important pour restaurer diverses fonctions neurologiques perdues. Un élément clé dans la mise en œuvre des dispositifs est le réseau de microélectrodes (MEAs pour MicroElectrode Arrays en anglais) servant d’interface avec les tissus nerveux. Les MEA jouent un rôle important dans les implants lors d’expérimentations chroniques, ils doivent être fiables, stables et efficaces pour l'enregistrement et la stimulation à long terme. Les propriétés électrochimiques et la compatibilité biologique des microélectrodes sont des facteurs essentiels qui doivent être prises en compte lors de leur conception et fabrication. La présente thèse traite de la conception et la fabrication de MEA en silicium micro-usiné à haute densité et en forme de pyramides qui sont destinés à l’enregistrement et la stimulation intracorticals 3D. Nous nous concentrons principalement sur les techniques de microfabrication des électrodes et le développement de procédure du revêtement de matériaux nécessaires pour la biocompatibilité et protection des dispositifs implantables. Nous élaborons des microélectrodes à hauteur variable pour enregistrer des signaux neuronaux, sans perdre la capacité de microstimulation et tout en maintenant des impédances de faibles valeurs. Cette caractéristique est obtenue en modifiant la géométrie et la composition de matériaux utilisés, ce qui facilite l'injection de charge et la résolution spatiale élevée. Nous présentons une nouvelle technique de micro-usinage 3D à nombre réduit de masques comparé aux techniques existantes. Nous décrivons la mise en œuvre d’un MEA à haute densité (25 électrodes / 1,96 mm2) et à différentes longueurs d’électrodes. En outre, une nouvelle technique de masquage à base de film sec a été développée pour obtenir de très petites surfaces actives pour les microélectrodes qui sont à hauteur variable. Nous avons réduit les étapes du procédé de masquage de 14 à 6 par rapport à la méthode classique de masquage utilisé dans la littérature. Nous avons ensuite effectué, pour la première fois, une croissance directe sélective de nanotubes de carbone sur les têtes de microélectrodes de longueurs variables en utilisant la technique du dépôt chimique en phase vapeur assisté par plasma (Plasma-Enhanced Chemical Vapor Deposition - PECVD).----------ABSTRACT Neuroprosthetic devices that can record neural activities and stimulate the central nervous system (CNS), called brain-machine interfaces (BMI), offer significant potential to restore various lost neurologic functions. A key element in functions restoration is Microelectrode arrays (MEAs) implanted in neural tissues. MEAs, which act as an interface between bioelectronic devices and neural tissues, play an important role in chronic implants and must be reliable, stable, and efficient for long-term recording and stimulation. Electrochemical properties and biological compatibility of chronic microelectrodes are essential factors that must be taken into account in their design and fabrication. The present thesis deals with the design and fabrication of silicon micromachined, high-density, pyramid-shaped neural MEAs for intracortical 3D recording and stimulation. The focused is mainly on the MEAs fabrication techniques and development of coating materials process required with implantable devices with an ultimate purpose: elaborate variable-height microelectrodes to obtain consistent recording signals from small groups of neurons without losing microstimulation capabilities, while maintaining low-impedance pathways for charge injection, high charge transfer, and high-spatial resolution by altering the geometries and material compositions of the array. In the first part of the thesis, we present a new 3D micromachining technique with a single masking step in a time and cost effective manner. A high density 25 electrodes/ 1.96 mm2 MEA with varying lengths electrodes to access neurons that are located in different depths of cortical tissue was designed and fabricated. Furthermore, a novel dry-film based masking technique for procuring extremely small active area for variable-height electrodes has been developed. With this technology, we have reduced the masking process steps from 14 to 6 compared to the conventional masking method. We have then reported for the first time a selective direct growth of carbon nanotubes (CNTs) on the tips of 3D MEAs using Plasma Enhanced Chemical Vapor Deposition (PECVD) that could enhance electrical properties of the electrodes significantly. The CNT coating led to a 5-fold decrease in impedance and a 600-fold increase in charge transfer compared with Pt electrode. Finally, we have highlighted the importance of the coating MEAs with bioactive molecules (Poly-D-lysine) and polyethylene glycol (PEG) hydrogels to minimize the immune response of the neural tissue to implanted MEAs by in vitro cell-culture tests

Direct growth of carbon nanotubes on new high-density 3D pyramid-shaped microelectrode arrays for brain-machine interfaces

Silicon micromachined, high-density, pyramid-shaped neural microelectrode arrays (MEAs) have been designed and fabricated for intracortical 3D recording and stimulation. The novel architecture of this MEA has made it unique among the currently available micromachined electrode arrays, as it has provided higher density contacts between the electrodes and targeted neural tissue facilitating recording from different depths of the brain. Our novel masking technique enhances uniform tip-exposure for variable-height electrodes and improves process time and cost significantly. The tips of the electrodes have been coated with platinum (Pt). We have reported for the first time a selective direct growth of carbon nanotubes (CNTs) on the tips of 3D MEAs using the Pt coating as a catalyzer. The average impedance of the CNT-coated electrodes at 1 kHz is 14 k. The CNT coating led to a 5-fold decrease of the impedance and a 600-fold increase in charge transfer compared with the Pt electrode

Toward an energy-efficient high-voltage compliant visual intracortical multichannel stimulator

ABSTRACT: We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode–tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a high-impedance microelectrode array driver (MED) output stage. The fourchannel SG produces rectangular, half-sine, plateau-sine, and other types of current pulse with stimulation current ranging from 2.32 to 220 μA per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode–tissue interface for ±13 V power supplies. The MED supplies different current levels with the maximum value of 400 μA per input and 100 μA per output channel simultaneously to 8–16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-μm CMOS and 0.8-μm 5-/20-V CMOS/double-diffused metal-oxidesemiconductor technologies. The measured dc power budgets consumed by low- and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test results with 0.9% phosphate buffer saline show the microelectrode impedance of 70 Ωk at 1 kHz

US Microelectronics Packaging Ecosystem: Challenges and Opportunities

The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.Comment: 22 pages, 8 figure